Difference between revisions of "Implementations"
Jump to navigation
Jump to search
(Created page with "= Blackbird = = Blackbird-II = = Caracara =") |
|||
(10 intermediate revisions by the same user not shown) | |||
Line 1: | Line 1: | ||
− | + | This page lists the known implementations of fun processors and SoCs. | |
− | = | + | = List of fun cores = |
− | = Caracara = | + | == Kiskadee == |
+ | A simple multicycle graph-reducer CPU. | ||
+ | |||
+ | [[File:Kisk.png |300px|frameless|Kiskadee]] | ||
+ | |||
+ | == Blackbird == | ||
+ | |||
+ | High-bandwidth memory interface. | ||
+ | ==== CPU ==== | ||
+ | [[File:Bbird.png |300px|frameless|Blackbird]] | ||
+ | |||
+ | ==== [[Tools | SoC]] ==== | ||
+ | [[File:BBSOC.png |300px|frameless|Blackbird SoC]] | ||
+ | |||
+ | == Blackbird-II == | ||
+ | |||
+ | fun graph reducer in a 3-stage pipeline. | ||
+ | |||
+ | [[File:Bbird2.png |300px|frameless|Blackbird-II]] | ||
+ | |||
+ | == Caracara == | ||
+ | |||
+ | under development |
Latest revision as of 09:59, 8 August 2022
This page lists the known implementations of fun processors and SoCs.
List of fun cores
Kiskadee
A simple multicycle graph-reducer CPU.
Blackbird
High-bandwidth memory interface.
CPU
SoC
Blackbird-II
fun graph reducer in a 3-stage pipeline.
Caracara
under development